Download Japanese from Zero! Download On Review for the Piano. Download Papillon P. Download Section Abyss Bk. Download Tales from Shakspeare, by C. And Ed. By William Archer] V. Download The Mariner of St. Download What Is an Insect? A Life of Janet Frame. Framing and packetization of bus cycles, successive storing of information concerning bandwidth requirements of the multiple subsystems and respective selection by two arbitration levels, turn out to be additional demanding features whether only a processor interface towards a plurality of target subsystems is really implemented.
From a logic point of view a boundary should anyway exist between a true communication system interface, more suitable for a computer network, and a simpler processor interface. A processor interface generally deals with transactions between a single microprocessor and a plurality of target devices appended to the processor bus.
Many examples have been already discussed above speaking about the prior art architectures. By comparison communication network interfaces as per the Applicant opinion the Sonics' computer bus exploit communication media in order to extend communication facilities to a plurality of processors and devices. In the framework of communication networks the most relevant problem to be solved at the interface level is that of how to regulate multiple accesses to the common media from the various contenders, in order to both avoid conflicts and meeting different bandwidth requirements.
This problem, anyway important, is not as much pressing in a simpler processor interface and can be solved by means of traditional arbitration methods like round-robin one, in case modified as per a variant of the present invention to improve performances with a distributed architecture.
Contrarily to Sonics' communication system and to computer network interfaces in gender, a processor interface takes great advantage from burst transactions. Burst is a sequence of bus transactions occurring on consecutive bus cycles and implying address increment or decrement. Resort to burst transactions in processor interfaces having a distributed architecture needs the solution of some incoming problems.
Bursts transactions are quite inapplicable in communication systems like the Sonics' invention, for the reason that the mechanism that supports bursts is inconsistent with mechanisms for distributing bandwidth through a particular policy of the accesses. More precisely the more bursts are long the more they are profitable for reducing subsequent latency this argument will be detailed later ; so by using long bursts or by frequent recourse to shorter bursts the TDMA Time Division Multiple Access method taken to fair distributing bandwidth is paralyzed.
It's useful to remind that Sonics' invention implements two level arbitration scheme where the first level of arbitration is a framed time-division-multiplexing arbitration scheme and the second level is a fairly-allocated round-robin scheme implemented using a token-passing mechanism: to say two TDMA methods. The main shortcoming of the Sonics' communication system has been outlined, that is to be unable to improve designs reuse and reduce time-to-market of relevant on-chip devices without introducing technical features typical of computer network interfaces.
In application addressed to usual microprocessor interfaces those features should appear like additional and too binding ones. The main purpose of the present invention is that to indicate a microprocessor, or local bus, interface having a modular distributed architecture towards user macro-cells encompassing a standardizable set of resources variously configurable in accordance with the needs of the macro-cells. Consequent main purpose of the invention is that to indicate an interface bus protocol able to manage in a transparent way the round-trip latency of communication between microprocessor and resources in order to avoid subsequent latency other than the initial delay and optimize burst transactions through a bus of the interface continuously shared among distributed resources.
Derived purpose of the invention is that to further specialize a main block of the distributed architecture in order to de-couple, as far as possible, the main block of the interface towards changes in the external microprocessor.
Another purpose of the invention is that to exploit in a profitable way a two clock domains synchronizer circuit, developed by the same Applicant, in the new context of the distributed interface. Further purpose of the invention is that to indicate a software facility for writing driver code of devices based on user macro-cells interfaced with the distributed microprocessor interface in subject.
Major benefits are driver reusability when a certain macro-cell has to be reused in a different context and easiness of development of new drivers starting from a driver skeleton referencing the standardizable set of resources indicated above.
To achieve said purposes the subject of the present invention is an interface between a microprocessor, or local bus, and user developed macro-cells having the modular and distributed architecture described in claim 1.
Main module and peripherals modules of the distributed interface of the present invention may be advantageously implemented like further macro-cells. The distributed interface of the present invention has a great impact on the new user developed macro-cells. The transfer of all those above mentioned resources into configurable peripheral modules of the microprocessor distributed interface allows a great uniform design of all genders of macro-cells, indifferently belonging to the user or the interface itself.
The development and interfacing of user macro-cells is made easier consequently and the designer can concentrate prevalently on the macro-cell function. Another advantage of the distributed interface of the invention, due to its high modularity, consists in furnishing a scalable architecture.
It is in fact convenient to provide the interface with the only peripheral modules whose resources are effectively exploited by the complex of user macro-cells. Moreover the distributed interface, thanks to the presence of a COMMON-BUS, has a number of interconnections between the main and peripheral modules not excessively high; that makes the structure suitable for FPGA bread-boarding implementation.
Because the proposed architecture is the same for both ASIC and FPGA, no changes are necessary changing the implementation technology, a rapid prototyping of an ASIC under development is possible consequently in order to explore the correctness of the design and speed up the time to market.
The distributed interface disclosed in the claim 1 , besides the standardizable peripheral resources, includes means expressly designed to optimize the data throughput across the overall interface.
Efficient burst transactions are promoted by including in each peripheral module a filling status calculator indicating residual room in the selected resource either for writing or reading, and by introducing in the main module companion means for elaborating the remote filling status received from a selected peripheral resource in order to compensate the subsequent latency other than the initial one. The presence of these means greatly helps the development of an efficient interface bus protocol, as it will be seen in the following.
A peculiarity of the interface in subject, largely derived from the use of filling status dedicated means, is the capability to conjugate a modular distribute architecture with skill in burst transactions, despite the fact that a COMMON-BUS shared among a plurality of resources force the main module to take initial latency whenever a selected resource changes by effect of arbitration.
The filling status dedicated means entirely support and prompt the interface bus protocol in the task of optimizing write burst transactions. The buffer in the main module allows anticipative read of a selected resource, both prefetchable and not, until the buffer is near full.
In this way the interface can be profitable employed for interfacing the widely diffused local buses obeying to Information Technology IT protocols, which require a backward acknowledge signal at each singular datum read in the buffer by the external processor.
At the end of a current transaction the data unread from the external microprocessor or generic bus master are purged from the buffer to assign an empty buffer at the successive requester. Being the buffer a traditional FIFO, the purged data should be definitively lost if also the peripheral resource connected to the buffer were a not prefetchable traditional FIFO. In that the advantage of the distributed architecture of the present interface is fully exploited.
Further advantageous architectural characteristic of the interface is that to have a second level of modularity inside the main module, as disclosed in the dependent claims.
To meet the second level of modularity, main module consists of a centralized circuit which controls various specialized circuits largely decoupled each other.
The centralized circuit collects most of the relevant events manifested on the two directions of the COMMON-BUS and on the external-bus, also collects the grant signals generated by an internal arbiter and in various significant points of the circuit.
This further enhanced architecture of the interface makes easier to change an external microprocessor or generic bus master without affecting the user macro-cells and the distributed interface other than a command decoder dedicated to cope with the new microprocessor and a sequencer acting on the external-bus. Another subject of the invention is an interface COMMON-BUS protocol which makes operative the interface of the claim 1 , as disclosed in the respective independent claims. The protocol of the invention works optimally with burst transaction because of its insensibility versus the subsequent latency, contrarily to the majority of the known protocol.
The goal is reached by tracing the filling status of remote peripheral resources locally to the main module. In this way the only latency in the transaction remains the unavoidable initial round trip delay. This method is necessary because while a microprocessor or generic bus master access to a peripheral resource is immediately known to the main module which manages the interface protocol and executes the filling status algorithms, a macro-cell access to the same resource becomes known to the manager only after the latency between the peripheral and the main module is elapsed.
A second specialized algorithm currently updates the first remote filling status received after the initial latency is elapsed by summing up the traced variation and subtracting a unity value each time a datum is transferred between the main module and the external bus master and the main module when the external bus master writes data into the main module or a read command is issued on the COMMON-BUS when the external bus master reads data from the main module.
In this way the updated filling status is a local image of the remote filling status as far as possible precise. Said local filling status is put at the disposal of the protocol to take immediate decisions concerning prosecution or termination of a burst transaction, without shortcoming of crossing the boundaries of the not prefetchable resource actually selected. The precision of the remote filling status anticipated locally to the main module is based on two assumptions. A first one is that the datum written from the external bus master to the main module is considered effectively transferred when the handshake for it has taken place at the interface between the external bus master and the main module.
In a similar way the datum read from a macro-cell connected to a peripheral resource is considered effectively read when the handshake for it has taken place at the interface between the external bus master and the main module. A second assumption is that the filling status locally anticipated in the main module is equal or pejorative with respect to the real one.
Both the assumptions are generally satisfied. Secondly, the variations in the remote filling status due to an interconnected macro-cell can only increase its value both in read more data to read and write more room to write data.
Furthermore, for question of convenience, the filling status is saturated at a value greater or equal to the maximum round-trip latency that a transaction kept on COMMON-BUS, being the value of the latency approximated at the upper integer. Advantageously the binary value expressing filling status saturated as indicated above, allows a precise visibility of the residual room on the resources either for writing or reading in the time window of the round trip latency, avoiding to exploit unnecessarily wider buses.
The modularity of the protocol matches the modularity of the hardware, consequently the various algorithms composing the protocol are easily assigned to as many separate circuit parts, both concerning main and peripheral modules, although mostly of the algorithms are charged to the main module. The protocol itself can be seen like a plurality of algorithms able to run concurrently and variously combined together by a supervisor algorithm to cope with different type of transactions arising from different cases of mastership of the external-bus in write or read.
This arrangement allows great advantages in terms of reusability of the design. The advantages of the hardware architecture are reflected in the protocol that, contrarily to known ones, charges minimally the macro-cells.
The philosophy of the distributed interface in subject is that to provide interfacing resources externally to the user macro-cells.
In line with this philosophy user macro-cells should be discharged also from the synchronization jobs. A synchronization problem arises when macro-cells belong to a clock domain different from that of the interface one. In case a peripheral resource interfacing macro-cells is a dual port RAM, or a FIFO, synchronization is generally carry out by the respective controller in a known way. On the contrary when peripheral resources are registers the known art synchronizers need some ad hock logic embedded in the macro-cells, other than the interface logic.
As far as synchronization concerns, the finalities of the distributed interface in subject are achieved with peripheral resources of register type by exploiting a separate invention subjected to a patent application in the name of the same Applicant. A two clock domains synchronization circuit is disclosed in that application.
The circuit has been expressly designed to be simply interposed between the two domains to be synchronized. It descends that ad hock logic embedded in the macro-cells is no more necessary.
Thanks to the owned peculiarity such a synchronizer becomes part of the distributed interface, from an architectural point of view, that because it offers to an interfaced macro-cell a synchronization service complementary to the service offered from the resource itself. Consequently any possible complication in adapting the disclosed synchronizer to the various type of registers is a matter confined inside the interface. The synchronization circuit can be advantageously seen as an independent element of a HDL list Hardware Description Language able to increase any more the modular design of the distributed interfaces when it operates in asynchronous way.
Further subject of the invention is a software facility for writing driver code for devices based on user macro-cells interfaced to a microprocessor through the distributed microprocessor interface of the claim 1 , as disclosed in the respective independent claims. The software facility is directed to a map file for assigning a different physical address to each symbolic address included in a declaration part collecting arguments of all the basic Functions building up the driver macro-cell by macro-cell.
The modular architecture of the distributed interface helps in writing absolute addresses of map file when the symbolic driver shall be multiple allocated or relocated. This makes free hardware designers to deliver drivers in symbolic code no address binding performed and test it after relocation, increasing the portability of the drivers themselves.
Summarizing, advantages of said software facility consist in the independence from the operating system specific calls and in the portability of the same drivers in different hardware Integration platform of reused macro-cells and software Operating System environments.
Said features are obtained by writing the low level drivers in terms of O. Then the low level drivers will be incapsulated from calls of the specific O. Further objects and advantages of the present invention will be made clear by the following detailed description of an embodiment thereof and the annexed drawings given for purely non-limiting explanatory purposes and wherein:.
With reference to FIG. These functions are aggregated in two main sets: TX and RX. The receiver side of the board gets ATM cells from the primary input RX, authenticates, stores and reassembles them in packets, and sends the packets to the proper destination through the local bus LB.
The reassembled segments form packets that are sent to the destination. Each macro-cells needs specific signals in order to be properly configured and controlled, e. On the contrary to a microprocessor interface of the prior art which need a consistent design embedded in the user macro-cells, because the architecture of the interface is not based on a consistent standardizable design outside the user macro-cells able to operate the interface in a way substantially application independent.
It differs from the embodiment of FIG. This means that some buses could not be physically present in the implementation but their function must be implemented e. Moreover the upstream buses are of type one 2 many one-to-many: only one driver.
Because of the particular tree like configuration of the distributed interface of the invention depicted in FIGS. In this case the bus layout is:. The ASIC implementation of a net of an upstream bus is a net buffered at any branch. The board implementation likely, under the high driving strength of pad and board drivers, does not require buffers. For the downstream buses, all solutions are possible, but the preferred one is the use of the so-called AND-Bus for active low signals and of the so called OR-Bus for active high signals.
The use of gate based bus prevents bus contention problems and moreover make portable the bus implementation from board to ASIC and vice-versa. Other entities, not shown in FIG. In the present FIG. A well experienced method that it is useful to follow, in part, for addressing peripheral resources in the non limiting example of the present invention is that disclosed in the Chapter 6 of PCI Local Bus Specification.
The addressing method used by the PCI is the most general and sophisticated used in the Information Technology area. As a consequence the minimum requirement for the DMI is to support such features and as, will be show in the next, to introduce some new ideas to enhance the interfacing with the resources embedded into the custom design.
The PCI case will be included as a particular case. Coming back to chapter 6 of the PCI specification there is that of providing a mechanism to proper configure the space address in order to allow:. Basing on these aims, the system designer is obliged to fill a list of the equipped resources, their individual address span and their properties as an example prefetchable or not characteristic, Memory Space or IO Space required mapping and so on.
The list is completed with some other fields, like: device identifier, vendor identifier, serial number, interrupt pin, latency, supported commands, status etc. This list has to be hardwired or downloaded into a set of register characteristic of the PCI.
The information contained into the Configuration Space Header of the PCI is used from the boot software at the boot time after the power-up to correctly boot, configure and handle said PCI interface. In particular, the boot software at the boot time after the power-up reads this Configuration Space Header to understand how to handle each resource.
At the same time it maps resources into physical memory by writing proper values into the so-called Base Addresses taking in account the requirements of each resource in terms of memory or IO space required and modality of access.
Devices that need less space are in any case allocated into 4 kbyte and the remaining space is void. Regarding the Memory Space this means that the minimum memory space allocation could be of 4 Kbyte.
Conversely the maximum one in unbounded So, the result of space configuration is an Address Map of the resources which subdivide the overall address space among them, each resource being identified by means of an absolute base address and the relative size.
A lot of divergences arise in respect of PCI standard concerning both resource addressing and structure of the configuration space. To understand the reasons of these differences is necessary to anticipate same details of the DMI architecture.
With a language used in the IT area they translates from linear address space to physical address space. Said registers are divided into two portions. In this last case a second level of address translation is executed.
In general is possible translating from a linear address space the one seen from the EBA accessing the DMI to a structured address space conform to the topology of the distributed interface and to the layered organization of leaves. This constitutes a peculiar aspect of the invention. Both sub-buses Leaf-Selector-Bus[ 7 : 0 ] and Address-Bus-root 2 leaf[ 31 : 0 ] are then forwarded to the cluster of peripheral leaves to make operative the second decoding step for addressing resources.
In such cases said second layer of address decode may be very simple. In such a case the second step of decoding is simply a check of the consistence of a certain low portion of the address sent on the Address-Bus-root 2 leaf[ 31 : 0 ] matches with the single address assigned to the fifo.
As seen above this table is similar to the PCI Predefined Header for the aspects regarding addressing. Finally, also the relative order of registers into the table can be altered. This is possible by an address translator embedded into the table itself. This makes the system reliable because the meaningful events for the various machines are homogeneous and easy to modify because the various machines are each other de-coupled.
In other words no direct communication take places between the mentioned machines. The three blocks enclosed in dashed rectangle in FIG. It is enough to redesign the only the plug-in module. As said in the case of FIG. Moreover, the macro-cell embeds four dashed boxes. First three boxes are collectively indicated as:. This function hereinafter will be referred also as application.
To interface the resources with the user macro-cell, each resource has a specific port set of data and control signals towards the user macro-cell. At this level a straightforward the connection is point to point protocol of interface is proposed.
Similar arguments can be used for other kinds of registers. The same arguments valid for resources of register type are still valid for resources of memory type. Again, the same arguments valid for resources of register type are still valid for resources of FIFO type. To do that this logic must be able of generating push signal and to monitor the FIFO status to be sure not to write when the FIFO is full otherwise written data are lost. In the operation, the purposes of the various hardware resources of the two FIG.
The resources of said standardizable set are individually configurable into a variety of sub-sets in accordance with specific needs of the respective interfaced macro-cells. It is useful to remind that in the known interface the resources are not standardizable, not provided with the interface, designed by users for their specific applications, and functionally embedded into user macro-cells.
The distributed microprocessor interface of the present invention has a great impact on the design of user macro-cells. Consequently all the advantages of the invention previously stated in the disclosure are plenty justified. With reference to FIGS. The architecture is specialized into standardizable sub-sets of resources individually configurable in accordance with specific needs of the respective interfaced macro-cells.
The three leaf distinguishing layers are:. Prefetchable referred to a resource means that a read performed on that resource has no side effects on the same resource. A resource is said to exhibit no side effect on read if, when a datum is read from that resource, that datum is still available to said resource, that is the read operation is not destructive.
Another example of prefetchable resource is represented by RAM memories. Not Prefetchable referred to a resource means that said resource exhibit side effect on read. A resource is said to exhibit side effect on read when a datum read from that resource is no longer available to said resource, that is the read operation is destructive.
In the next FIGS. Due to these reasons not all layers are required to be simultaneously present. Depending on the application, only the required layers are instantiated; this saves area in implementations. With reference to the FIG. Exhaustive explanation concerning the various Layer ports will be give later. The inputs are four, each selected by a respective strobe asserted. In this case the incoming signals and related strobes are as in the following:.
At the end one can appreciate that:. Reconnecting to the previous developed arguments, we remember that the power-on configuration software produced a memory map of the allocated resources indicating their base addresses.
For this aim the following information is required. This is done before the synthesis because of the high optimization both in terms of area and performance resulting from eliminating unused logic. The length being expressed in number of bit word and the check consisting of a comparison between the actual value of the address for read or write transaction with the boundary of the resource of register or memory type.
A burst transaction is either a read or write transaction for moving a certain number of sequential data words. Binary values of these two fields are not yet pieces of information suitable to carry out efficient burst transactions, they had to be further elaborated in view of latency to obtain a filling status indicator managed by COMMON-BUS protocol for reaching the efficiency goal. Further arguments about filling status indicator need that latency of communication and efficiency of protocols be preliminary discussed in view of the prior art.
The following considerations help in the comprehension. In said architecture a block CLBI Centralized Local Bus Interface is connected to a burst read port and to a burst write port of two macro-cells embedding FIFOs, and to other macro-cells by a bussed port no burst capable devoted to configuration and control of the macro-cells.
The architecture of FIG. The round trip latency of communication between block CLBI and a selected port is defined as the time expressed in clock cycles elapsing from beginning to the end of the chain of events listed in the following. Analogue considerations are valid for other typologies of transaction. Latency of communication in the above round trip path is mainly due to input and output sampling and to an intrinsic delay of control FSMs in both blocks CLBI and selected macro-cell.
As a consequence, the latency can change when the type of the interfaced resource register, memory or FIFO changes and when the type of executed transaction change read or write. This happens because in the described scenarios, operation of the control FSMs embedded in block CLBI and macro-cells can be different this depends on implementation.
Consider for example a burst transaction to write read a FIFO. It is clear that when block CLBI issues the write command it is not informed of the true residual room on the memory either for writing reading until the RDTPL time is elapsed, presupposing to have activated check means at beginning of write read transaction. When the relevant information arrives to CLBI block, perhaps that in the meanwhile the boundary of the FIFO is crossed due to a burst too long and some data are definitely lost.
Dual considerations are valid for reading. To avoid this drawback, as happen in the majority examples of the known art, a read and a write threshold have to be set at a certain clock pulses before the two boundaries of the FIFO are reached. The crossing of a threshold causes a feedback message towards block CLBI for stopping the burst and regulating consequently. Furthermore, the threshold-crossing detector in the macro-cell also detects when the boundary of the FIFO is reached, in case it generates another feedback message to the block CLBI that definitively stops the residual transaction.
Usually the IP vendors let the threshold management charged to the users. A smart threshold management policy is that to put the threshold prudently away from the boundary of the FIFO and when the threshold is crossed the returned message is used to stop the burst.
Since that point the access is continued with slower handshake method in which two consecutive data are time spaced by a number of clock pulses at least equal to the round trip latency RDTPL.
The majority of known protocols that govern read and write burst transactions between a unique block CMI and peripheral resources embedded in the macro-cells, are referable to the above arguments. Those protocols exhibit a not optimum efficiency in managing burst transactions but the drawback doesn't particularly worsen the overall bus efficiency mainly because the connection through the bus are point to point. On the contrary in the distributed interface of the present invention, in which a COMMON-BUS is shared among a cluster of peripheral resources that in turn access to it, a not optimum efficiency accumulated when servicing the various resources can negatively affect the performance of the interface.
Bus efficiency is a pure number spanning from zero to one for measuring how a bus protocol is fast in transferring data. To define the bus efficiency let's consider a device interfaced bus agent with a defined bus interface. Be the bus driven by a golden bus agent; the golden bus agent is a device which drives the bus in the most efficient way defined in the bus protocol definition e. Where, N is the number of exchanged data and TLi is the total initial latency of the transaction latency to start the transaction up to first data exchanged while TLs is the total subsequent latency latency spent to exchange subsequent data in the transaction up to the end.
In that hypothesis the Efficiency increases for N increasing. A known way to increase Efficiency is to recur to a burst transaction exploiting a pipelined architecture like buffering data into a FIFO.
The longer is the FIFO buffer, the higher is the efficiency. In this case the system has only initial latency TLi, that can also be seen as a delay. Being latency TLi constant, to increase Efficiency 1 is useful to increase the residual burst length N as over TLi clock cycles as possible but this increases the communication delay.
Maximum increasing of the residual burst length would implicate the full exploiting of the pipelined architecture, but the previous arguments about the necessity of introducing thresholds show that this is not possible. In conclusion, known protocols are not optimum because not able to take delay TLi without introducing subsequent latency TLs.
Delay is unavoidable due to physical reasons. This is also valid for digital delays measured in clock cycles. Conversely subsequent latency TLs due to both protocol and architectures could be avoided or at least drastically reduced by innovative solutions.
Returning to the invention, as stated in precedence, the COMMON-BUS transfer protocol makes use of a properly dimensioned filling status of the accessed resource for achieving the efficiency goal.
Saturation, applied by proper hardware, also prevents the filling status to become not meaningful. Saturation is even successfully applied when filling status is involved in arithmetic operation; in this case the result might be not meaningful due to overflow. To avoid the overflow problems calculating the filling status it is enough to append a 0 as MSB to the filling status before executing arithmetic operations on it and then saturating the result to the original bit width.
In the first case the filling status indicator is said to be static, in the second it is said to be random. At cycle C i the filling status takes the value I i. This is because, in the meanwhile, the user macro-cell connected to the FIFO might have been writing it, as a result the number of readable data might have been increased this number is random. The gain in efficiency using filling status instead of thresholds is that the length of the burst is always dimensioned to the effective boundary of the resources.
This is a smart solution quite advantageous in presence of a shared bus because it manages the round trip delay in a transparent way avoiding subsequent latency, this means that round trip delay has no effects on burst efficiency, contrary to the threshold used in known protocols. Let us exemplify the notion of saturated filling status and its effect on the efficiency by means of an example in which the dimension of the filling status is deliberately lower than round-trip latency.
We also consider the worst case where no new room is created by an application which read the FIFO in the meanwhile. When the protocol of the distributed interface will be discussed it will be appreciated that block DMI MAIN further elaborates the received filling status, summing up or subtracting the contribute of the actual transaction, in order to gain the capability of stopping a burst exactly at the boundary of the FIFO. Further consideration is that block DMI MAIN forwards a pure query to the selected resources just before a write, or read, transaction to have the filling status returned and so appreciating the maximum permissible burst length consequently.
Then 4 consecutive writes are executed and DMI MAIN block subtracts one to the local filling status at each write; as the fourth datum is sent the local filling status is zero. This condition is detected by opportune protocol means which stop write because it interprets the condition, as there is no more room to write the FIFO. We suppose that a new query is sent at the first wait cycle after completion of the fourth write, precisely at the 5 th clock cycle from the beginning of writes.
So in the case of the example the first datum is effectively written in the resource at the 5 th clock cycle from the start of the first write, successive second, third and fourth data are written at the 6 th , 7 th , and 8 th clock cycle. As a consequence, at the arrival of the fourth datum the updated filling status matches the correct binary 2 binary 4 is held constant for both the first and second data time by effect of saturation.
The query sent at the 5 th clock cycle reach destination at the 8 th clock cycle and at the 9 th clock cycle the correct filling status binary 2 is sent back to the DMI MAIN block. If the FIFO were longer than 6 words the four additional wait states should be equally introduced, because they depend from the difference between RDTPL and saturated filling status, and the burst also written in fits and starts as above.
In conclusion the depicted transaction takes 22 clock cycles, 8 clock cycles of latency RTPDL are unavoidable, 6 clock cycles last for writing the 6 words, the remaining 8 clock cycles represent a subsequent latency that can be zeroed by a better dimensioned filling status.
In case longer burst and FIFO are considered, for example 64 words, from the mechanism described above it descends that block DMI MAIN takes 8 additional clock cycles for each 4 words written, and clock cycles for 64 words. Let us now introduce a second more fitting example whose aim is to demonstrate that when the filling status is dimensioned to be saturable at the value of latency RTPDL, than the additional wait states are not more necessaries.
Starting from this position, at the end of the initial query long RTPDL time the returned filling status is saturated at binary 7.
Now the write burst starts to write 8 consecutive words as many expressed by filling status 0,. Suppose that to meet with a more efficient communication and to have a constant monitor of the residual space in the FIFO, the single write command be coupled with a query for a returned filling status, as effectively implemented in the protocol of the invention.
It can be argued that just at the end of the eighth word written, filling status relative to the query coupled with the first word arrives to the DMI MAIN block and still contains the saturated binary 7.
So a new write burst of eight words starts avoiding interruption and without taking subsequent latency. Bursts after bursts the boundary zone of the FIFO is reached, so from a certain point in time the returned filling status is no more saturated but begins to decrease. The same conclusion is valid in case the filling status is saturated at a value greater than RDTPL latency, or not saturated at all. This is because the only condition that must be verified is the visibility of a valid filling status during the RDTPL time window.
Precisely a saturated filling status effectively corresponding to a memory room to write greater than or equal to the returned value, or a not saturated filling status having a decreasing value as the writes being in progress. In the not limiting examples of FIGS. The Point-to-Point-Buses sketched in continuous lines carry data, the sketched in dashed lines carry controls.
This set of functions mainly consists of configuration setting, command issuing, events counting, status retrieving and event trapping. These functions define at fine grain level, for the leaf side portion of the DMI architecture, a superset of the functions depicted for prior art interfaces. The types have been defined studying several real applications and allow effective interfacing of macro-cells for all configuration and control problems. Consequently only the exact required number of registers of the exact required type is synthesized; this saves area in the implementation.
From an addressing point of view each register in the layer implemented with a bit word is seen as an address. If all available registers are used, the address map of this layer is a sequence of contiguous addresses. If some registers are not implemented not configured for implementation by generics some holes result in the contiguous address space. The length is expressed in number of bit word. The table indicates that the maximum lengths of reading and writing bursts for a certain register are not equal; that because not all the registers are both readable and writeable.
In both cases the final value becomes a filling status indicator managed by the protocol governing the distributed interface.
The read value, in case opportunely saturated, is the filling status indicator at the current writing transaction. The case presented in FIG. The two blocks are bi-directionally connected through respective Point-to-Point-Buses. In each Point-to-Point-Bus some sub-buses are present.
The ones sketched in continuous lines carries data, the ones sketched in dashed lines carries controls. In the case presented in FIG. ViolinistEmma Sweeney guests on one track, Trio Seven. For his new album, City, McCallum steps even further into the world of electronica, whilst still maintaining that magical combination of both acoustic and electronic instruments that gives his music such a distinctive sound.
However, two things make City stand out from his previous work. First, the addition of vocals and second, the decision to bring in London based drummer and producer, Richard Spaven, who he met during his time playing with Cinematic Orchestra, not only to perform, but to co-write and produce the album all tracks are co-written by McCallum and Spaven apart from City. North Star, featuring Sharlene Hector, was written the old fashioned way, after studio computers decided to take an unscheduled rest.
His Naim debut, Distilled, was a series of beautiful instrumental soundscapes and glorious melodies that owed as much to dance music as it did to jazz.
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